The more one hears of verification, the less one understands what it means. In our cover story, reflecting our April theme of "verification as the heart of design," the authors emphasize that the designer's ultimate goal-first-pass silicon success-can be accomplished only by paying careful attention to a comprehensive verification strategy. "Comprehensive" and "strategy" are catchwords for a process that, in the end, can be labeled as "I know it when I see it" verification. The authors offer a very good divide-and-conquer approach that starts with block-level functional verification, followed by full-chip functional and timing verification.
Other methods are being proposed. One, featured on the EEdesign site (www.eedesign.com/features/exclusive/OEG20020225S0074), involves using a complete block of IP, which includes hardware, software API, verification code, protocol checkers and monitors, and documentation. That structure allows encapsulation of the IP block-a complete "vertical slice" of IP, according to Zaiq director and principal consultant Al Czamara.
It appears, however, that these new methods and the tried-and-true verification tricks are not enough. Our cover-story authors claim that in the final stages of the IC design process, it is customary to conduct a final set of audits to provide evidence of design robustness. Here is where it gets interesting. The combination of a robust verification process and proper audits should guarantee that the design is sound from a functional as well as a manufacturing point of view, say the authors.
Indeed, it does the designer little good to implement a verification strategy only to end up with a design that passes muster but can't be fabbed. What may be needed is something on the order of an Underwriters' Laboratories seal of approval for system-on-chip designs. Only after the design passes the audits of an independent testing organization-in this case, that body may be a design house's separate internal quality assurance department-can customers be assured that what they buy will work.
A lot of that depends on the acceptance of doing million-gate designs in a standardized fashion. More and more efforts are being exerted to come up with standard operating procedures in the SoC world. Those efforts include initiatives by VSIA, VCX and Accellera.
Each organization is attempting to standardize on a portion of the design process-VSIA on how IP blocks are put together, VCX on how IP blocks are bought and sold, and Accellera on what language to use when working with IP. All three touch on verification issues and have even set up working groups to develop strategies.
But none is thinking about the end product and whether it can assure verified, audited and guaranteed IP blocks for use. Unless some industry body starts thinking along the lines of a UL-based seal of approval for SoC design, the Babel of verification languages and the verification conundrum will likely continue unabated.
If they are to make verification the heart of design, designers need to be assured that their SoC has been verified as robust by an independent body that is qualified to put its figurative stamp on the design.
Any takers?
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Copyright © 2002 CMP Media LLC
4/1/02, Issue # 14154, page 4.
